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19-0009; Rev 2; 8/95
UAL IT MAN TION K T VALUA A SHEE E DAT LLOWS FO
18-Bit ADC with Serial Interface
____________________________Features
o Low Supply Current: 60A (Normal Operation) 1A (Sleep-Mode Operation) o 0.006% FSR Accuracy at 16 Conv/sec o Low Noise: 15VRMS o Serial I/O Interface with Programmed Output for Mux and PGA o Performs up to 100 Conv/sec o 2pA Input Current o 50Hz/60Hz Rejection
_______________General Description
The MAX132 is a CMOS, 18-bit plus sign, serial-output, analog-to-digital converter (ADC). Multi-slope integration provides high-resolution conversions in less time than standard integrating ADCs, allowing operation up to 100 conversions per second. Low conversion noise provides guaranteed operation with 512mV full-scale input range (2V/LSB). A simple 4-wire serial interface connects easily to all common microprocessors, and twos-complement output coding simplifies bipolar measurements. Typical supply current is only 60A and is reduced to 1A in sleep mode. Four serially programmed digital outputs can be used to control an external multiplexer or programmable-gain amplifier. The MAX132 comes in 24-pin narrow DIP and wide SO packages, and is available in commercial and extended temperature grades. High resolution, compact size, and low power make this device ideal for data loggers, weigh scales, data-acquisition systems, and panel meters.
MAX132
______________Ordering Information
PART MAX132CNG MAX132CWG MAX132C/D MAX132ENG MAX132EWG MAX132MRG TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -55C to +125C PIN-PACKAGE 24 Narrow Plastic DIP 24 Wide SO Dice* 24 Narrow Plastic DIP 24 Wide SO 24 Narrow CERDIP**
________________________Applications
Remote Data Acquisition Battery-Powered Instruments Industrial Process Control Transducer-Signal Measurement Pressure, Flow, Temperature, Voltage Current, Resistance, Weight
* Contact factory for dice specifications. ** Contact factory for availability and processing to MIL-STD-883.
________________Functional Diagram
__________________Pin Configuration
TOP VIEW
CREFCS SCLK EOC DIN DOUT
CREF+
V+ 602k
+5V
CS 1 DIN 2 DOUT 3
24 V+ 23 BUF OUT 22 INT OUT 21 INT IN
BUF OUT INT OUT INT IN REF+ REF4.7nF
SCLK 4 OSC2 5 OSC1 6 P0 7 512mV INPUT P1 8 P2 9 P3 10 EOC 11 DGND 12
MAX132
20 CREF19 CREF+ 18 REF+ 17 REF16 AGND 15 IN LO 14 IN HI 13 V-
MAX132
P0 P1 P2 P3 OSC1
AGND IN LO IN HI VDGND OSC2 -5V
DIP/SO ________________________________________________________________ Maxim Integrated Products 1
Call toll free 1-800-998-8800 for free samples or literature.
18-Bit ADC with Serial Interface MAX132
ABSOLUTE MAXIMUM RATINGS
Supply Voltage V+ to DGND ..............................................-0.3V < V+ < +6.0V V- to DGND ................................................+0.3V < V- < -9.0V V+ to V- ............................................................................+15V Analog Input Voltage (any input).....................................V+ to VDigital Input Voltage .....................(DGND - 0.3V) to (V+ + 0.3V) Continuous Power Dissipation Narrow Plastic DIP (derate 8.70mW/C above +70C)....478mW Wide SO (derate 11.76mW/C above +70C)..............647mW Narrow CERDIP (derate 12.50mW/C above +70C) ..688mW Operating Temperature Ranges MAX132C_ _ .......................................................0C to +70C MAX132E_ _ ....................................................-40C to +85C MAX132MRG .................................................-55C to +125C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = 5V, V- = -5V, DGND = AGND = IN LO = REF- = 0V, REF+ = 545mV, RINT = 602k, CINT = 0.0047F, CREF = 0.1F, fCLK = 32,768Hz, 60Hz mode, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER ACCURACY Resolution Zero Error Integral Nonlinearity Rollover Error Conversion Time Input Voltage Range CONDITIONS (Note 1) VIN HI = 0V (Notes 2, 3) (Note 4) TA = +25C TA = TMIN to TMAX TA = +25C TA = +25C TA = TMIN to TMAX 63 2 12 0.009 0.25 512 10 250 0.032 0.50 3.0 3.1 1.5 5 5.5 -4.5 0.0061 0.0168 0.0061 0.0168 125 -65 -60 10 -10 2 0 0.0015 0 MIN TYP MAX 18 0.0076 0.0168 0.006 0.010 0.032 UNITS Bits % of FSR % of FSR % of FSR ms mV pA % of FSR V % of FSR V ppm/C ppm/C V V % of FSR % of FSR A A A A A A
fCLK = 32.768Hz IN HI to IN LO, for specified accuracy TA = +25C Leakage Current IN HI, IN LO TA = TMIN to TMAX VCM = 500mV Common-Mode Rejection Ratio IN HI = IN LO VCM = 3.0V Common-Mode Range IN HI = IN LO Read-Zero 50Hz/60Hz Range RMS Noise TA = +25C Zero-Reading Drift (Note 3) Scale Factor Temp. Coefficient (Note 3) POWER REQUIREMENTS Positive Supply Voltage Negative Supply Voltage TA = +25C VIN HI = 400mV, V- = -5.0V, Positive Supply Rejection 4.5V V+ 5.5V TA = TMIN to TMAX TA = +25C VIN HI = 400mV, V- = 5.0V, Negative Supply Rejection -5.5V V- -4.5V TA = TMIN to TMAX Positive Supply Current Digital input = 0V or V+ Negative Supply Current Digital input = 0V or V+ Digital Ground Supply Current Digital input = 0V or V+ Positive Sleep-Mode Current Digital input = 0V or V+ Negative Sleep-Mode Current Digital input = 0V or V+ Digital Ground Sleep-Mode Current Digital input = 0V or V+
15 0.15
4.5 -5.5 0.003 0.003 0.003 0.003 60 -35 -25 1 -1 0
2
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18-Bit ADC with Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 5V, V- = -5V, DGND = AGND = IN LO = REF- = 0V, REF+ = 545mV, R INT = 602k, CINT = 0.0047F, CREF = 0.1F, fCLK = 32,768Hz, 60Hz mode, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER DIGITAL SECTION DOUT, IOUT = -1mA Output High VOH DOUT, IOUT = -100A EOC, P0-P3, IOUT = -100A Output Low Input High Input Low Input Current Input Capacitance VOL VIH VIL IIN CIN DOUT, IOUT = 1.6mA EOC, P0-P3, IOUT = 100A Referred to DGND, 4.5V V+ 5.5V, CS, DIN, SCLK Referred to DGND, 4.5V V+ 5.5V, CS, DIN, SCLK CS, DIN, SCLK, and DOUT when three-stated CS, DIN, SCLK, and DOUT when three-stated 10 2.4 0.8 500 5 3.5 4.0 4.0 4.3 4.5 4.7 0.1 0.1 0.4 0.4 V V V nA pF V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX132
INTERFACE TIMING
(Test Circuit of Figure 1, Figure 2, V+ = 5V, V- = -5V, DGND = AGND = 0V, TA = +25C, unless otherwise noted.) (Note 3) PARAMETER CS Lead Time CS Lag Time SCLK High Time SCLK Low Time CS High Pulse Width DIN to SCLK Setup Time DIN to SCLK Hold Time DOUT Access Time from Three-State Data Valid DOUT Disable Time to Three-State Delay to P0-P3 High Delay to P0-P3 Low Note 1: Note 2: Note 3: Note 4: SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 See Figure 4 230 230 See Figure 3 CONDITIONS MIN 500 400 400 300 1 0 200 320 60 320 350 350 TYP MAX UNITS ns ns ns ns s ns ns ns ns ns ns ns
18-bit accuracy achieved by averaging multiple conversions. Maximum deviation from best straight-line fit. Guaranteed by design, not tested. Difference in reading for equal positive and negative inputs near full scale.
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3
18-Bit ADC with Serial Interface MAX132
__________________________________________Typical Operating Characteristics
ERROR vs. COMMON-MODE INPUT VOLTAGE (VIN LO-AGND)
MAX132-01
50Hz/60Hz READ-ZERO OFFSET vs. VREF
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 50Hz MODE 0 0.5 1.0 VREF (V) 1.5 2.0 60Hz MODE
MAX132-02
50Hz/60Hz READ-ZERO OFFSET vs. TEMPERATURE
1.4 60Hz MODE, VREF = 545mV 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) 50Hz MODE, VREF = 655mV
MAX132-03
0.05 0 ERROR (% OF FSR) -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -4 -3 -2 -1 0 1 2 3 COMMON-MODE VOLTAGE (V) 4 IN HI = IN LO
4.5 READ-ZERO OFFSET (% OF FSR)
1.6 READ-ZERO OFFSET (% OF FSR)
SUPPLY CURRENT vs. CRYSTAL FREQUENCY
MAX132-04
FULL-SCALE ROLLOVER ERROR vs. VREF
MAX132-05
NOISE vs. NUMBER OF SAMPLES AVERAGED
MAX132-06
140 120 SUPPLY CURRENT (A) 100 80 60 40 20 0 -20 -40 0 50 100 150 200 250 300 VV+
0.10 ROLLOVER ERROR (% OF FSA) 0.08
20
15 0.06 NOISE (VRMS)
10
0.04
0.02
5
0 350 0 0.5 1.0 1.5 2.0 2.5 CRYSTAL FREQUENCY (kHz) VREF (V)
0 0 10 20 30 40 50 NUMBER OF SAMPLES AVERAGED
______________________________________________________________Pin Description
PIN 1 2 3 4 5 6 7 8 NAME CS DIN DOUT SCLK OSC2 OSC1 P0 P1 FUNCTION CHIP SELECT Input has 3 functions: 1) When low, selects IC for communication; 2) on rising edge, loads input shift register data into one of the command registers; 3) on falling edge, loads data from one of the output registers into the output shift register. When CS is high, DOUT is high impedance. Serial Data In, D7 first bit in. Data is clocked into the register on the rising edge of SCLK. Serial Data Out, D7 first bit out. Data is clocked out at the falling edge of SCLK. High impedance when CSis high. Serial Clock Input. On SCLK's rising edge, data is shifted into the internal shift register through DIN. On SCLK's falling edge, data is clocked out of DOUT. Oscillator Output 2 is normally connected to a 32,768Hz crystal. Do not connect with external clock source. Oscillator Input 1 is normally connected to a 32,768Hz crystal, or may be connected to an external clock. User-programmable output bit 0--programmed through the serial port. User-programmable output bit 1--programmed through the serial port.
4
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18-Bit ADC with Serial Interface
_________________________________________________Pin Description (continued)
PIN 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME P2 P3 EOC DGND VIN HI IN LO AGND REFREF+ CREF+ CREFINT IN INT OUT BUF OUT V+ FUNCTION User-programmable output bit 2--programmed through the serial port. User-programmable output bit 3--programmed through the serial port. End of Conversion Output goes high at end of conversion. Digital Ground--power-supply return Negative Supply, nominally -5V Positive Analog Input Negative Analog Input Analog Ground Negative Reference Input Positive Reference Input Positive Reference Capacitor connection Negative Reference Capacitor connection Integrator Input. Connect the integration capacitor between INT IN and INT OUT. Integrator Output. To minimize noise, this pin should drive the capacitor's outside foil (negative end). Buffer-Amplifier Output drives the integrator resistor. Positive Supply, nominally +5V
MAX132
0.1F 20 CREF1 4 11 2 3 CS SCLK EOC DIN DOUT REF+ REF7 8 9 10 19 CREF+ V+ 24 23 22 21 18 17 16 15 14 13 12
+5V 2.5V 602k 120k
MAX872
BUF OUT INT OUT INT IN
4.7nF
100k
40.2k
MAX132
P0 P1 P2 P3 OSC1 6
AGND IN LO IN HI VDGND OSC2 5 15pF
512mV INPUT -5V
32,768Hz 15pF
Figure 1. Test and Typical Application Circuit
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5
18-Bit ADC with Serial Interface MAX132
____________Functional Description
The MAX132 integrates the input voltage for a fixed period of time, then deintegrates a known reference voltage and measures the time required to reach zero. Good line rejection is achieved by setting the (input) integration time equal to one 50Hz or 60Hz period. The MAX132 has a 50Hz/60Hz mode selection bit that sets the integration time to 655/545 clock periods, respectively, so that 50Hz/60Hz rejection is obtained with a 32,768Hz crystal. The MAX132 is tested and guaranteed at a 16 conv/sec throughput rate. Figure 1 shows the basic MAX132 application circuit, with component values selected for 16 conv/sec . For applications that don't require 50Hz/60Hz rejection, the MAX132 will operate up to 100 conv/sec at reduced accuracy (typically 0.012% FSR nonlinearity, or 13 bits). In these applications, the 50Hz mode is recommended because of its longer (655 count) integration time. See Increased Speed section.
__________Analog Design Procedure
Input Voltage Range and Input Protection
The recommended analog full-scale input range is 512mV. Performance is tested and guaranteed at 512mV full scale, corresponding to a 2V/LSB resolution at 18 bits. Resolution is defined as follows: Re solution Volts / LSB
[
]
= VIN (FS) / 262,144
which corresponds to 2V/LSB resolution at 18 bits. Consult the Typical Operating Characteristics for Noise vs. Number of Samples Averaged and other important operating parameters. Note how accuracy depends on common-mode input voltage (common mode is defined here as |VIN LO - AGND|). For optimum performance, set the analog input full-scale between 470mV and
t5 CS t3 t1 SCLK t6 DIN t8 DOUT MSB OUT B6-B1 LSB OUT MSB IN t7 B6-B1 LSB IN t9 t10 t4
t2
P0-P3 t11, t12
Figure 2. Serial-Mode Timing
+5V +5V
3k DOUT 3k DGND CL DOUT CL DGND DOUT 3k DGND 10pF DOUT
3k
10pF DGND
a. High-Z to VOH (t8)
b. High-Z to VOL (t8)
a. VOH to High-Z (t10)
b. VOL to High-Z (t10)
Figure 3. Load Circuits for Access Time
6
Figure 4. Load Circuits for Disable Time to Three-State
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18-Bit ADC with Serial Interface
660mV for 60Hz mode operation or between 390mV and 550mV for 50Hz mode operation. The pseudodifferential input voltage is applied across pins 14 and 15 (IN HI, IN LO), and can range to within 2V of either supply rail. The inputs IN HI and IN LO lead directly to CMOS transistor gates, yielding extremely high input impedances that are useful when converting signals from a high input source impedance, such as a sensor. Input currents are only 2pA typical at +25C. Figure 6 shows an RC filter at the input to optimize noise performance. Fault protection is accomplished by the 100k series resistance. Internal protection diodes, which clamp the analog inputs from V+ to V-, allow the channel input pins to swing from (V- - 0.3V) to (V+ + 0.3V) without damage. However, if the analog input voltage at the pins IN HI or IN LO exceed the supplies, limit the current into the device to less than 1mA, as excessive current will damage the device.
MAX132
60Hz Mode : VREF = or 50Hz Mode : VREF =
(545 counts) (512) VIN(FS) ) 262,144 (655 counts) (512) VIN(FS) ) 262,144
The recommended reference voltage range is 500mV to 700mV. The MAX132 is tested with the nominal 545mV reference voltage in 60Hz mode. Use amplifiers or attenuators (resistor dividers) to scale other full-scale input signal ranges to the recommended 512mV fullscale range. References outside the recommended range may be used with a degradation of linearity. A reference voltage from 200mV to 500mV will result in a lower signalto-noise ratio; a reference voltage from 700mV to 2V will increase the rollover error. The MAX872 2.50V reference, with its 10A supply current, is ideally suited for the MAX132. Figure 7 shows how 2.50V can be divided to obtain the desired reference voltage. The reference input accepts voltages anywhere within the converter's power-supply range; however, for best performance, neither REF+ nor REFshould come within 2V of the supplies.
Reference Voltage Selection
The reference voltage sets the analog input voltage range. For the nominal 512mV full-scale input range, a 545mV reference voltage is used for the 60Hz mode and a 655mV reference voltage is used in the 50Hz mode. The reference voltage can be calculated as follows:
CREF+
REF+ DE
CREF DE
REF-
CREF-
RINT BUFFER
INT IN
CINT
INT OUT
MAX132
X8 8pF INT IN HI DEDE+ BUFFER INTEGRATOR Z1+ x 8 DE+ DE64pF COMPARATOR 1
REST AGND INT IN LO INT
TO DIGITAL SECTION
COMPARATOR 2
Figure 5. Analog Section Block Diagram
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18-Bit ADC with Serial Interface MAX132
Differential Reference Inputs and Rollover Error
The main source of rollover voltage error is due to common-mode voltages. This error is caused by the reference capacitor losing or gaining charge to stray capacitance. A positive signal with a large commonmode voltage can cause the reference capacitor to gain charge (increase voltage). In contrast, the reference capacitor will lose charge (decrease voltage) when deintegrating a negative input signal. Rollover error is a direct result of the difference in reference to positive or negative input voltages. With the recommended reference capacitor types, the worst-case rollover error is 0.01% of full-scale. Connect REF- to AGND to minimize rollover error. As outlined in the reference section, reference voltages below 500mV also contribute to rollover errors.
Oscillator Circuit
The internal oscillator is typically driven by a crystal, as shown in Figure 8, or by an external clock. If an external clock is used, connect the clock to OSC1 and leave OSC2 floating. The duty-cycle can vary from 20% to 80%. The typical threshold voltage is approximately 2V. For proper start-up, a full +5V CMOS-logic swing is required. The oscillator frequency sets the conversion rate. Use 32,768Hz for applications that require 50Hz or 60Hz line rejection. This frequency yields 16 conv/sec. The same clock frequency can be used to reject both line frequencies because the MAX132 integrates for a different number of clock cycles in its 50Hz and 60Hz modes. In each case, the MAX132 integrates for a single complete line cycle (20ms for the 50Hz mode, 16.67ms for the 60Hz mode). Refer to the Increased Speed section for operation at higher conversion rates.
External Components
+5V 24 100k 512mV V+ 14 0.1F 15 IN HI
MAX132
IN LO 18 +545mV
The MAX132 requires an integrator resistor (RINT) and capacitor (CINT), a reference capacitor (CREF), and a crystal. All MAX132 tests are performed with a 32,768Hz crystal frequency. The crystal frequency, reference voltage, and integrator current determine the values of RINT and CINT.
16 AGND 17 REFV13 -5V
REF+
Crystal Figure 8 shows the internal oscillator drive circuitry used with external crystals. The two external capacitors provide DC bias at start-up. The 15pF capacitors shown are typical values. The actual capacitance will vary, depending on the crystal manufacturer's recommendation and board layout.
Figure 6. MAX132 Input Circuit
+5V 5pF 120k 1M
+5V 5pF
MAX872
2.5V 150k OSC1 6 15pF OSC2 5 15pF
MAX132
REF+ 1F
100k
40.2k
REF-
Figure 7. Dividing MAX872 to Generate the MAX132's Reference Voltage
8
Figure 8. MAX132 Internal Oscillator Drive Circuitry
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18-Bit ADC with Serial Interface MAX132
Table 1. Crystal Frequencies and Integrator Capacitors for 50Hz to 60Hz Operation
Conv/sec 16 32 48 64 80 96 Crystal Freq. (Hz) 32,768 65,536 98, 304 131,072 163,840 196,608 CINT/60Hz (pF) 4700 2700 1800 1200 1000 820 CINT/50Hz (pF) 6800 3300 2000 1500 1200 1000 Resistor (k) 602 602 602 602 602 602
t INT = or
545 fOSC
, for 60Hz mod e
Note: Capacitor values are for a 3.0V integrator swing. Manufactures of miniature quartz resonators include: Epson of America C-2 (through-hole), MC-306 (SMD) Phone: (310) 787-6300; Fax: (310) 782-5320
655 , for 50Hz mod e fOSC The integrator capacitor's dielectric absorption directly affects integral nonlinearity. High-quality metal-film capacitors are recommended in the following order of preference: polypropylene, polystyrene, polycarbonate, and polyester (Mylar). The polyester capacitor will generate some integral nonlinearity. To minimize noise, INT OUT should drive the outside foil (negative end) of the capacitor. Manufacturers of polypropylene capacitors include Sprague (715P), Panasonic (ECQ-P), Roderstein (KP1835), Wima (FKP), and CSF Thompson (PL/PS). t INT =
Integrator Resistor The integrator resistor sets the maximum integrator output current for the integrate phase. A 602k low-noise, metal-film integrator resistor is recommended for use with reference voltages between 545mV and 655mV. Best linearity is achieved when the integration current (IINT) does not exceed 2.5A. For other reference voltages, select RINT as follows:
RINT = and IINT = VREF RINT VREF 2.5A < IINT < 0.5A
Reference Capacitor The reference capacitor must be small enough to fully charge from a discharged state on power-up in reasonable time, and large enough so the charge does not droop excessively during a conversion. The reference capacitor is normally 0.1F for all oscillator frequencies. For applications that require a physically smaller capacitor, the equation below will maintain CREF proportionality:
CREF = 0.0033 fOSC
Integrator Capacitor The oscillator frequency, integrator resistor, and integrator capacitor set the maximum integrator output voltage swing for full-scale reading. The integrator voltage swing is about 3V and should not come within 2V of either supply rail to avoid saturation. A 602k integrator resistor and a 4.7nF integrator capacitor are recommended with a clock frequency of 32,768Hz. If different clock frequencies are used, select CINT using the following equations:
CINT = and (VIN(FS) ) (t INT ) , where 1V < VSWING < 3.5V; (RINT ) (VSWING )
The reference capacitor must have low leakage, since it stores the reference voltage while floating during the deintegrate phase. Any leakage or charge loss during this phase changes the scale factor and will cause an error. Appropriate metal-film capacitors recommended for their low-leakage characteristics1 are (in this order): polypropylene (up to +105C, large size), teflon (suitable for use up to +125C, large size), polystyrene, polycarbonate, and polyester. At temperatures above +85C, capacitor leakage may affect accuracy. In such cases, increasing the value of CREF up to 50% and more will help at the expense of longer start-up time at power-on. The start-up time is proportional to CREF and can be estimated by: t START - UP = CREF (F) x 10 x 100k
1 Pease, R.A., "Understanding Capacitor Soakage to Optimize
Analog Systems," EDN, October 13, 1982, p.125. _______________________________________________________________________________________ 9
18-Bit ADC with Serial Interface MAX132
___________________Digital Interface
Serial data at DIN is sent in 8-bit packets and is shifted into the internal 8-bit shift register with each rising edge of SCLK. The data is then latched into either command input register 0 or command input register 1, as determined by the LSB of the data sent, and is latched on the rising edge of CHIP SELECT (CS) Data is clocked out of the selected output register on each falling edge of SCLK. D7(MSB) must be the first data bit to be shifted in and is the first bit to be shifted out. Output data is shifted out at the same time command data is shifted in. Command data must be clocked in on the previous 8-bit read-write cycle to receive conversion data in the present cycle. Since there is no internal power-on reset, initialize the MAX132 immediately after power-up to insure correct operation. Table 2 defines each bit of five registers: the two command input registers, output register 0, output register 1, and the status output register.
REGISTER INSTRUCTION (DATA IN) OUTPUT DATA CYCLE 1 START, READ STATUS CYCLE 2 READ HIGHER BITS CYCLE 3 READ LOWER BITS CYCLE 4 START, READ STATUS
OUTPUT STATUS REGISTER (EOC, POLARITY, B2-B0)
REGISTER 1 ( B11-B18)
REGISTER 0 ( B3-B10)
Figure 9. Instruction and Data Sequencing
Read-Zero Bit The read-zero bit allows the ADC to calibrate on command for zero offset. The read-zero bit, when set to 1, internally shorts the inputs; when a start-conversion command is given, the zero error is converted. Subtract the results from the standard external measurement conversion when the read-zero conversion ends. If the read-zero bit is set to 0, the converter measures the voltage between IN Hl and IN LO once a start bit is given. Take a new zero reading periodically and whenever the ambient temperature, the reference voltage, or the common-mode input voltage are changed.
Command Input Register 0
Register-Set Bits Data bits D1 and D2 of command register 0 (RS1 and RS0) determine the data to be read on the data bus. These bits select which register outputs data to the bus. Table 3 defines the bit values that determine which register is read on the next cycle (Figure 9).
Table 3. Register Set-Bit Definitions
RS1 0 0 1 1 RS0 0 1 0 1 DEFINITIONS Selects Register 0; output for data bits B3-B10 Selects Register 1; output for data bits B11-B18 Selects Register 2; output status for data bits B0-B2, polarity, sleep, integrating, EOC, and collision bit Invalid data
Table 2. Register Map of Input and Output Data
REGISTER "1" "0" DATA BIT D7 Start Convert Returns to 0 at EOC Set P3 Output B10 B18 MSB "1" "0" Collision D6 50Hz 60Hz Set P2 Output B9 B17 EOC D5 Sleep Awake Set P1 Output B8 B16 Integrating Input D4 D3 D2 D1 D0
Command Input Register 0 Command Input Register 1 Output Register 0 RS1 = 0, RS0 = 0 Output Register 1 RS1 = 0, RS0 = 1 Output Status Register RS1 = 1, RS0 = 0 *Note: Refer to Table 3. 10
Read Zero Don't Care RS0* Read VIN Set P0 Output B7 B15 Sleep Awake Don't Care Don't Care Don't Care B6 B14 -Polarity B2 +Polarity B1 B5 B13 Don't Care B4 B12 1 B3 B11 RS1* 0
Not No Collision Converting Integrating
B0 LSB
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18-Bit ADC with Serial Interface
Averaging 2 or 3 read-zero measurements provides the most accurate read-zero value. Perform a read-zero sequence whenever a large change in the input voltage is expected.
Sleep Bit When the sleep bit is set to 1, (bit D5 in command input register 0), the low-power sleep mode starts when EOC returns high. In sleep mode, the supply current is typically 1A and the oscillator shuts down. The interface remains active and data can be read. When exiting sleep mode, the analog circuitry needs time to stabilize before the next conversion starts. Accomplish this by writing a dummy instruction to emerge from sleep mode, and wait at least one conversion cycle before writing a start instruction. 50Hz/60Hz With a 32,768Hz crystal, the 50Hz/60Hz bit sets the integrate period equal to one line cycle for 50Hz/60Hz environments. When D6 (in command input register 0) is set to 0, the integrate count is an integer multiple of 60Hz (32,768Hz/60Hz = 546 counts). When D6 is set to 1, the integrate input count is an integer multiple of 50Hz (32,768Hz/50Hz = 655 counts). Achieve the greatest AC rejection by adjusting the integration period for 50Hz or 60Hz.
Start Conversion Bit The start conversion bit (D7) in command input register 0 initiates a conversion when set to 1. The MAX132 immediately starts a conversion, stops at conversion end, and then waits for the next start-bit command. A start instruction is needed to initiate each conversion. To initiate a continuous data stream, write a separate start command for each conversion in three ways:
1) Wait longer than a known conversion time and then write another start command. 2) Poll either the EOC status register bit or the EOC line to determine conversion end and start time for the next conversion. EOC becomes 1 at conversion end at count 0000 of the conversion counter (Figure 10). 3) Set the start bit to 1 before a conversion end. The internal conversion counter is then checked for its count. If the count is 0000 (EOC = 1), a new conversion starts and the conversion counter is set to 0001. The start bit resets to 0 after 5 clock cycles. The MAX132 will not check the start bit again until the conversion counter returns to a 0000 count. This means a start command can be given any time after 0005 internal conversion count; the next conversion starts when the counter returns to 0000.
MAX132
RESET 0000 0001
60Hz INT START 0111 INTEGRATE 50Hz mode 655 545 60Hz mode
CHOP 659 667 DE-1 679 MAX SOFT OVERRANGE AREA (SEE TEXT)
1346 X8-1 264
1600 DE-2 38
1638 X8-2 145
1783 DE-3 40
1823
1970
2017
RESET EVENTS 2047 0000
X8-3 147
DE-4 47
ZERO INT 30
ZERO INT
INT OUT 545 MAX
LATCH INTERNAL CONVERSION DATA LATCH EOC
Figure 10. Conversion Timing (Negative Input Shown)
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11
18-Bit ADC with Serial Interface MAX132
Table 4. Overrange Values for Resolution Used
Bits Used B18-B3 B18-B2 B18-B1 B18-B0 Resolution Bits 15 16 17 18 Soft Overrange Start Value 34,880 69,760 139,520 279,040 Hard Overrange Maximum Value 43,805 87,610 175,220 350,440
Command Input Register 1
User-Programmable Output Bits P0 to P3 Command input register 1 always has data bit D0 = 1. Data bits D4 to D7 of command register 1 control the states of the user-programmable output pins P0 to P3, respectively (Table 2). These four outputs can be used to control an external multiplexer, programmable gain amplifier, or other devices.
Output Registers
Output data is the sum of system offset (read zero) plus the results of the external input voltage measurement.
Table 5. Output Values for 16-Bit Resolution (Offset Corrected)
Input +640mV +576mV +545mV +512mV +448mV +384mV +320mV +256mV +192mV +128mV +64mV +15V 0 -15V -64mV -128mV -192mV -256mV -320mV -384mV -448mV -512mV -545mV -576mV -640mV Hexadecimal Reading +A000 +9000 +8840 +8000 +7000 +6000 +5000 +4000 +3000 +2000 +1000 +0001 +0000 -FFFF -F000 -E000 -D000 -C000 -B000 -A000 -9000 -8000 -77C0 -7000 -6000 Decimal Counts +40960* +36864* +34880* +32768 +28672 +24576 +20480 +16384 +12288 +8192 +4096 +1 0 -1 -4096 -8192 -12288 -16384 -20480 -24576 -28672 -32768 -34880* -36864* -40960* Negative Full Scale Negative Reference Voltage Positive Reference Voltage Positive Full Scale Comment
Register 0 Register 0 contains the low-byte (bits B3-B10) conversion data. New data is available after EOC goes high. Access register 0 by setting RS0 and RS1 to 0. Register 1 Register 1 contains the high-byte (bits B11-B18) data. Data is in a twos-complement format where the polarity bit is a 1 for negative polarity data. Access register 1 by setting control bits RS0 = 1 and RS1 = 0 when writing to the command input register.
Status Register
Bits B0-B2 The B0, B1, and B2 bits are located in the status register. At the end of each conversion these bits are updated and read back from the status register. For full 18-bit resolution, use bits B0-B2. Average multiple results to increase accuracy. The polarity bit information is necessary to determine if the reading is not in overrange (Tables 4 and 5). Integrate Bit The integrate (INT) bit is set to 1 at the beginning of the integration phase and becomes 0 at the end. Poll INT to determine the earliest time the input can be changed without affecting the conversion. End-of-Conversion Bit The end-of-conversion (EOC) bit signals conversion status. If EOC is 1, the conversion is complete and the ADC waits in zero-integrate mode at time = 0000 for the next start instruction. A conversion cycle has 2048 counts. EOC becomes 1 at count 0000 and 0 at count 0001. Collision Bit The collision bit warns the microprocessor (P) that the register's data was changed during the read cycle. A collision occurs if the internal result latches on the falling edge of CS, causing the collision bit to be set to 1 on the rising edge of the next CS. This occurs because these two pulses are asynchronous. Once the status register is
* Soft Overrange Operation Note: The MAX132 exhibits additional errors when operating in the soft overrange area. Operation in this region is not included in the specifications. The soft overrange values listed in Table 5 do not include error correction. 12
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18-Bit ADC with Serial Interface
read, the collision bit is automatically reset to 0. To determine collision status, read the status register collision bit before and after reading output registers 0 and 1. Collisions will not occur if a conversion's read cycle is completed before the next conversion begins. commands must be synchronous with the clock. As a result, the delay between zero-crossing and switch actuation can exceed one clock cycle. A "residue" voltage that represents unwanted extra counts in the conversion result is left on the capacitor, while the integrator's output continues past the zero crossing. Dual-slope converters ignore this residue voltage error. However, the multislope MAX132 inverts, amplifies, and deintegrates the residue, canceling the extra counts by driving an up/down counter in the opposite direction. This process of measuring and accounting for the residue can be repeated for the successively smaller errors remaining after each deintegration. (Deintegration is simply an integration of VREF, with polarity chosen so the integrator output ramps toward zero.) The MAX132, for example, executes three cycles in which the residue is inverted, multiplied by eight, and deintegrated (Figure 10).
MAX132
Sequence Counter and Results Counter
A binary sequencing counter controls the conversion phase's sequencing (or timing). In integrate phase, both start and stop occur at preset counts. The deintegration phases start at predetermined counts, but are terminated when the comparator detects zero crossing at the integrator output. The results counter accumulates counts during all deintegrate phases. It is an up/down binary counter, with the count direction determined by the deintegration polarity. In the first deintegrate phase, the results counter counts by 512. Since the second deintegrate phase deintegrates a residual voltage multiplied by 8, the results counter increments or decrements by 64 during this phase. It increments or decrements by 8 during the third deintegrate phase, and by 1 during the fourth deintegrate phase. The results counter content transfers to the results register at each conversion end.
Integrate Phase
The MAX132 integrates the input signal by connecting the integrator's noninverting input to IN LO, and the buffer input to IN Hl. The integration period is 545 counts for 60Hz mode and 655 counts for 50Hz
Deintegrate Phase
The integrator capacitor's voltage polarity at the end of integrate phase determines the polarity of the first deintegration phase. The first deintegration phase ends when the comparator detects that the integration capacitor has been discharged. The MAX132 then goes into a rest phase, where both the buffer input and the integrator's noninverting input are connected to AGND, integrating the system offset. Near the end of the maximum allowable deintegration period, the integrator capacitor voltage polarity is again sampled, resulting in either a positive or negative deintegrate cycle.
Overrange Indication
B18 is not strictly an overrange bit. This 19th bit is necessary to exploit the converter's full range, and to ensure that a full 18-bit result can be achieved after a zero reading has been deducted. The actual overrange value is a function of the number of bits of resolution used. Table 4 lists the overrange values for different resolutions. The MAX132 has two overrange levels (Figure 10 and Table 4). The first level is a soft overrange that is set by the user. Overrange is arbitrarily set at a value, preferably less than the 279,040 (including any zero offset) raw counts soft limit. A nonlinearity step of about 64 counts occurs at raw count 279,040 and again at 330,240 counts. The second level is a hard overrange with a maximum value of 350,440 counts. Attempts to deintegrate values greater than this will result in a value of 350,440 counts.
Rest Phase
A rest phase follows each deintegrate phase. The rest phase starts when the integrator crosses zero and ends when the maximum count for that deintegration phase has been reached.
____Multislope Conversion Phases
Multislope conversion allows 350,440 counts with a clock frequency of only 32.768kHz. After zero-crossing, the main comparator (with some delay) sends a signal to the digital control section, which then terminates the deintegrate period by issuing commands to the analog switches. This action entails further delay because the
First Times-Eight Phase
When the zero crossing is detected at the end of the deintegrate phase, deintegration continues until the next clock cycle. This causes the integrator to overshoot zero crossing slightly, leaving a small residual voltage on the integration capacitor. The first timeseight (X8) phase inverts and multiplies this residual by a factor of 8.
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13
18-Bit ADC with Serial Interface MAX132
Second Deintegrate Phase
The second deintegrate phase deintegrates residual voltage on the integration capacitor that has been through the X8 phase. Since the voltage across the integration capacitor has been multiplied by 8, each deintegration clock cycle corresponds to 1/8 of one clock cycle during the first deintegration. Although either the 50Hz or 60Hz mode can be used, complete rejection of 50Hz or 60Hz normal-mode noise at conversion rates above 16 conv/sec is impossible. Use the 50Hz mode when operating at more than 16 conv/sec, irrespective of the local line frequency. The 50Hz mode uses a slightly longer integration time than the 60Hz mode, and generally gives lower-noise performance. Table 1 lists the crystal frequencies and integrating capacitor values for the 50Hz and 60Hz modes for various conversion rates, although the 50Hz mode is recommended for clock rates above 32,768Hz. The raw data can be used where highest accuracy is not required, and the least significant bits can be ignored. At 96 conv/sec, the accuracy is 13 bits. Improvements in accuracy can be gained by averaging both the data and the zero readings, although data averaging compromises the converter's speed performance. To maximize throughput, take zero readings only when necessary, i.e., when the common-mode voltage changes. It is not normally necessary to take a zero reading after every data reading as an excessive number of zero readings reduces the converter's effective speed.
Additional Times-Eight and Deintegrate Phases
At the end of the second and third deintegration phases, the device performs a X8 multiplication of the residual voltage left on the integration capacitor. After each of these X8 multiplications, a deintegration occurs, resulting in a second, third, and fourth deintegration phase. Each time the residual voltage on the integration capacitor is multiplied by 8, the following deintegration has 8 times finer resolution.
Zero-Integrate Phase
The zero-integrate phase zeros out the integrator to prepare for the next integration (Figure 10). This phase occurs at the beginning and end of each conversion. At power-up, or in the hold mode prior to a conversion, the MAX132 continues to zero integrate until a conversion starts. When a conversion starts in 60Hz mode, another 111 clocks of zero integrate are completed before the beginning of a conversion. In 50Hz mode, only one additional zero integrate is performed before the conversion starts. An additional 20 clocks of zero integrate occur at each conversion end.
Noise Reduction
To minimize noise, each supply must be bypassed to GND with a 0.1F capacitor. A ground plane should also be placed under the analog circuitry. Use the RC network at the inputs as shown in Figure 6. Also refer to the section "Noise Reduction Techniques" in the notes for the MAX132 evaluation kit. To minimize the coupling effects of stray capacitance, keep digital lines as far from analog components and lines as possible. Also, connect the integrator capacitor's outside foil to the INT OUT pin to minimize stray capacitive coupling. If possible, keep the digital interface inactive while the MAX132 is converting.
__________Applications Information
Extended Delays Between Conversions
An extended delay between conversions can degrade the subsequent conversion result due to capacitor droop and internal offset/common-mode voltages. The initial reading may be off by 4 to 6 counts in a 15-bit configuration. When the delay between conversions exceeds 2 seconds (either because of a slower conversion rate or the use of sleep mode), it is recommended that the first reading after this delay be discarded.
Ratiometric Measurements
Figure 11 shows an application to measure temperature ratiometrically with an RTD sensor. The voltage drops across the RTD sensor and the 250 reference resistor are generated by the same current source. The voltage of the sensor (VS) is fed directly into the differential inputs, and the voltage drop across the reference resistor (VR) is brought into the differential reference inputs. The relationship of these voltages is ratiometric and unaffected by the actual current. The MAX132's output is proportional to VS divided by VR, independent
Increased Speed
The MAX132 is tested with a 32,768Hz clock frequency, which results in 16 conv/sec. Up to 96 conv/sec may be achieved with higher clock frequencies and some changes in component values, as shown in Table 1. Operation at higher conversion rates reduces accuracy, and care must be taken to get the best results.
14
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18-Bit ADC with Serial Interface
of the overall accuracy of the current source. The current source delivers 2mA, resulting in about 500mV across the 250 resistor--suitable to fit the MAX132's 512mV full-scale range. Note that the accuracy of the reference resistor (0.1%) sets the circuit's accuracy. The power consumption of the RTD sensor is small (0.5mW), minimizing errors caused by self-heating. to the MAX132. It provides an algorithm for serial communication when the P port does not have a predefined serial interface protocol (i.e., SPITM or MicrowireTM). The routine sends command data (TxByte) to the MAX132 while concurrently collecting the MAX132's output register data (selected by the previous write cycle). Note that a write is required before each read to change the next output register to be read, and that the subroutine must be repeated three times to read the output status register, Output Register 0, and Output Register 1.
MAX132
Interfacing to a P Parallel Port
Figure 12 shows a high-level software subroutine for reading output/status data and writing command data
+5V
-5V
+5V
IN
0.1F
10F
10F
0.1F
IC1
13 24 VSERIALDATA INTERFACE 2k CHIP SELECT DATA IN DATA OUT CLOCK 1 2 3 4 11 7 VR 250 0.1% 8 9 10 14 15 RW1 RTD PT100 CS DIN DOUT SCLK EOC PG0 PG1 PG2 PG3 IN HI IN LO DGND VS RW2 RW1, RW2 WIRE RESISTANCE 12 AGND 16 OSC1 V+ BUF OUT INT OUT INT IN 23 22 21 19 20 0.1F REF+ IN REF- IN OSC2 18 17 5 32,768Hz 6 4.7nF 600k
MAX872
OUT GND
4.096V
IC2 MAX132
CREF+ CREF-
Figure 11. Ratiometric Configuration Using the Differential Reference Inputs
SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
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15
18-Bit ADC with Serial Interface MAX132
___________________Chip Topography
WAIT UNTIL EOC PIN IS HIGH CLEAR SCLK CLEAR CS
SCLK DOUT DIN CS V+ BUF OUT INT OUT
INT IN
WRITE DIN132 FROM TxByte's MSB
OSC2
SET SCLK
CREFCREF+
READ DOUT132 INTO RxByte's LSB
OSC1 PG0
0.186" (4.72mm)
CLEAR SCLK
REF+ REF-
SHIFT RxByte LEFT SHIFT TxByte LEFT
PG1
REPEAT 8 TIMES
PG2 EOC PG3 DGND 0.144" (3.66mm) VIN HI AGND IN LO
SET CS RETURN RxByte
Figure 12. MAX132 Read/Write Algorithm
TRANSISTOR COUNT: 2799 SUBSTRATE CONNECTED TO V+
16
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